| Jan 12, 2024 |
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(Nanowerk News) Moore’s Law, a fundamental scaling principle for electronic devices, forecasts that the number of transistors on a chip will double every two years, ensuring more computing power — but a limit exists.
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Today’s most advanced chips house nearly 50 billion transistors within a space no larger than your thumbnail. The task of cramming even more transistors into that confined area has become more and more difficult, according to Penn State researchers.
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In a study published in the journal Nature (“Three-dimensional integration of two-dimensional field-effect transistors”), Saptarshi Das, an associate professor of engineering science and mechanics and co-corresponding author of the study, and his team suggest a remedy: seamlessly implementing 3D integration with 2D materials.
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Key Takeaways
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Moore’s Law, predicting the doubling of transistors on a chip every two years, faces limitations due to space constraints on current chips.
A novel approach involving 3D integration with 2D materials is proposed to overcome these constraints, enabling more transistors and functionalities.
Monolithic 3D integration, a method of fabricating semiconductor devices, promises higher density and space efficiency without the need for microbumps used in traditional methods.
The new method significantly reduces the process temperature, preserving the integrity of silicon-based chips and making it compatible with 2D materials.
This advancement in semiconductor technology not only aligns with Moore’s Law but also introduces additional functionalities, potentially transforming the electronics industry.
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| Penn State researchers demonstrated 3D integration of semiconductors at a massive scale, characterizing tens of thousands of devices using 2D transistors made with 2D semiconductors, enabling electronic gadgets to possibly become smarter and more versatile. (Image: Elizabeth Flores-Gomez Murray, Materials Research Institute)
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The Research
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In the semiconductor world, 3D integration means vertically stacking multiple layers of semiconductor devices. This approach not only facilitates the packing of more silicon-based transistors onto a computer chip, commonly referred to as “More Moore,” but also permits the use of transistors made from 2D materials to incorporate diverse functionalities within various layers of the stack, a concept known as “More than Moore.”
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With the work outlined in the study, Saptarshi and the team demonstrate feasible paths beyond scaling current tech to achieve both More Moore and More than Moore through monolithic 3D integration. Monolithic 3D integration is a fabrication process wherein researchers directly make the devices on the one below, as compared to the traditional process of stacking independently fabricated layers.
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“Monolithic 3D integration offers the highest density of vertical connections as it does not rely on bonding of two pre-patterned chips — which would require microbumps where two chips are bonded together — so you have more space to make connections,” said Najam Sakib, graduate research assistant in engineering science and mechanics and co-author of the study.
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Monolithic 3D integration faces significant challenges, though, according to Darsith Jayachandran, graduate research assistant in engineering science and mechanics and co-corresponding author of the study, since conventional silicon components would melt under the processing temperatures.
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“One challenge is the process temperature ceiling of 450 degrees Celsius (C) for back-end integration for silicon-based chips — our monolithic 3D integration approach drops that temperate significantly to less than 200 C,” Jayachandran said, explaining that the process temperature ceiling is the maximum temperature allowed before damaging the prefabricated structures. “Incompatible process temperature budgets make monolithic 3D integration challenging with silicon chips, but 2D materials can withstand temperatures needed for the process.”
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The researchers used existing techniques for their approach, but they are the first to successfully achieve monolithic 3D integration at this scale using 2D transistors made with 2D semiconductors called transition metal dichalcogenides.
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The ability to vertically stack the devices in 3D integration also enabled more energy-efficient computing because it solved a surprising problem for such tiny things as transistors on a computer chip: distance.
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“By stacking devices vertically on top of each other, you’re decreasing the distance between devices, and therefore, you’re decreasing the lag and also the power consumption,” said Rahul Pendurthi, graduate research assistant in engineering science and mechanics and co-corresponding author of the study.
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By decreasing the distance between devices, the researchers achieved “More Moore.” By incorporating transistors made with 2D materials, the researchers met the “More than Moore” criterion as well. The 2D materials are known for their unique electronic and optical properties, including sensitivity to light, which makes these materials ideal as sensors. This is useful, the researchers said, as the number of connected devices and edge devices — things like smartphones or wireless home weather stations that gather data on the ‘edge’ of a network — continue to increase.
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“’More Than Moore’ refers to a concept in the tech world where we are not just making computer chips smaller and faster, but also with more functionalities,” said Muhtasim Ul Karim Sadaf, graduate research assistant in engineering science and mechanics and co-author of the study. “It is about adding new and useful features to our electronic devices, like better sensors, improved battery management or other special functions, to make our gadgets smarter and more versatile.”
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Using 2D devices for 3D integration has several other advantages, the researchers said. One is superior carrier mobility, which refers to how an electrical charge is carried in semiconductor materials. Another is being ultra-thin, enabling the researchers to fit more transistors on each tier of the 3D integration and enable more computing power.
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While most academic research involves small-scale prototypes, this study demonstrated 3D integration at a massive scale, characterizing tens of thousands of devices. According to Das, this achievement bridges the gap between academia and industry and could lead to future partnerships where industry leverages Penn State’s 2D materials expertise and facilities. The advance in scaling was enabled by the availability of high-quality, wafer-scale transition metal dichalcogenides developed by researchers at Penn State’s Two-Dimensional Crystal Consortium (2DCC-MIP), a U.S. National Science Foundation (NSF) Materials Innovation Platform and national user facility.
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“This breakthrough demonstrates yet again the essential role of materials research as the foundation of the semiconductor industry and U.S. competitiveness,” said Charles Ying, program director for NSF’s Materials Innovation Platforms. “Years of effort by Penn State’s Two-Dimensional Crystal Consortium to improve the quality and size of 2D materials have made it possible to achieve 3D integration of semiconductors at a size that can be transformative for electronics.”
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According to Das, this technological advancement is only the first step.
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“Our ability to demonstrate, at wafer scale, a huge number of devices shows that we have been able to translate this research to a scale which can be appreciated by the semiconductor industry,” Das said. “We have put 30,000 transistors in each tier, which may be a record number. This puts Penn State in a very unique position to lead some of the work and partner with the U.S. semiconductor industry in advancing this research.”
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