Nanotechnology Now - Press Release: Avera Semi and OCP Announce New Open, Physical Interconnect Specification to Efficiently Connect Chiplets

Home > Press > Avera Semi and OCP Announce New Open, Physical Interconnect Specification to Efficiently Connect Chiplets

Abstract:
Bunch of Wires (BoW) specification, developed in conjunction with members of the OCPs Open Domain-Specific Architecture (ODSA) sub-project, to be made open and publicly available.

Avera Semi and OCP Announce New Open, Physical Interconnect Specification to Efficiently Connect Chiplets

Amsterdam, Netherlands | Posted on September 26th, 2019

Avera Semi and the Open Compute Project Foundation (OCP) today announced the availability of the Bunch of Wires (BoW) 0.7 specification for evaluation proposal to enable a broader understanding and participation in the development of the 1.0 specification. The BoW specification defines a chiplet-to-chiplet physical interconnect for power- area- and cost-efficient data transport between chiplets. Avera Semi has developed the specification in cooperation with Aquantia, Netronome, GLOBALFOUNDRIES and Xilinx, as a part of the Open Domain-Specific Architecture (ODSA) sub-project in the OCP.

The exponential growth of data and compute-intensive applications at scale require the development of new domain-specific architectures for compute, networking and storage applications. These heterogeneous architectures will combine general purpose compute and accelerators such as GPUs, FPGAs, SmartNICs, Persistent Memory and other domain-specific programmable devices. These architectures will need to be customized and cost-efficient across a wide range of performance and form factors.

Chiplet-based designs that combine heterogeneous processing elements in a single package are a promising approach to developing these domain-specific architectures. The ODSA Project aims to create an open interface between chiplets, so that best-in-class chiplets from multiple vendors can be combined to create custom products.

The overarching benefits of BoW enable efficient data movement between chiplets in heterogeneous designs. In many applications, BoW can be leveraged to build multi-chiplet products without software driver involvement. The BoW specification aims to offer a solution that combines interface design simplicity with the ability to use low-cost, multi-chiplet packaging technologies. The ease of design adds the ability to be implemented across a wide range of manufacturing process nodes, promoting heterogeneous design. Reduced wire count enables BoW technology to be used with low-cost packaging technology.

BoW provides a real value to our industry, enabling multi-chip solutions to interoperate with each other, said Mark Kuemerle, Fellow, Integrated Systems Architecture, Avera Semi. Unlike any existing standard, BoW provides solutions from the highest bandwidth with complex packaging to more moderate bandwidth with the simplest cost effective packaging.

The proposal for this specification was first revealed at ODSA workshops and presented in greater detail at the 2019 IEEE Hot Interconnects Symposium. This proposal adds greater detail to the material discussed in those presentations. The release of this proposal, available today, gives new companies an opportunity to participate in creating a 1.0 draft proposal. For more information on the OCP ODSA sub-project visit, https://www.opencompute.org/wiki/Server/ODSA.

Supporting Quotes:

“The BoW and ODSA proposal addresses fundamental obstacles impacting standardization and specification of low power interfaces,” said Ted Letavic, vice president and senior fellow at GF. “With the growing importance in platform innovations, our clients can benefit from BoWs low-power and simple interface design combined with the ability to use low-cost multi-chiplet technology.

The semiconductor industry has reached the unanimous conclusion that Chiplet-based systems are the future of silicon SoCs. The creation of BoW specification, a super-efficient die-to-die interface , is very timely to provide the industry a common interoperable interface for Chiplets,said Ramin Farjadrad, CTO/VP of PHY Technologies at Marvell Semiconductor. Such common interface can enable many applications such as artificial intelligence, autonomous vehicles and 5G networks.

“The Bunch of Wires interface offers a low-cost inter-chiplet interface for package aggregation

and die disaggregation applications with multiple packaging technologies, said Bapi Vinnakota OCP ODSA workgroup lead. The proposal has been developed cooperatively by the members of the ODSA project. We are pleased to have it available at the ODSA wiki for review and further discussion to support its further development.”

####

About Avera Semi
Avera Semi provides application-specific integrated circuit (ASIC) semiconductor solutions that deliver system-level differentiation for next-generation applications. The company was established in 2018 and is a wholly owned subsidiary of GLOBALFOUNDRIES.

For more information, please click here

If you have a comment, please Contact us.

Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.

Bookmark: