(Nanowerk Spotlight) Advances in semiconductor technology have reached a critical turning point. Silicon-based transistor technology, central to electronics, faces increasing limitations due to the fundamental quantum properties of silicon at extremely small scales. Moore’s Law, predicting that computing power doubles approximately every two years, is nearing its practical and physical limits.
Researchers and industries are now exploring alternative materials and technologies capable of surpassing these boundaries. Recent innovations involving two-dimensional (2D) materials and novel integration methods present compelling pathways for extending semiconductor capabilities beyond traditional silicon-based approaches.
A collaborative study (Advanced Materials, “Scalable Van Der Waals Integration of III-N Devices Over 2D Materials for CMOS-Compatible Architectures”) involving researchers from Soongsil University and Samsung Advanced Institute of Technology in South Korea has demonstrated an innovative integration technique that merges 2D materials with group III-Nitride (III-N) semiconductor devices in ways compatible with existing silicon-based technology.
This approach is significant because it maintains compatibility with current semiconductor manufacturing processes, crucial for practical industry adoption.
The core technology of this advancement, called fluidic-assisted self-alignment transfer (FAST), enables precise and scalable integration of electronic components onto substrates through van der Waals (vdW) forces—weak attractive forces effective at very small scales.
Using these forces, researchers successfully integrated III-Nitride-based devices, specifically Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) and micro-light-emitting diodes (micro-LEDs), onto graphene and molybdenum disulfide, both 2D materials with outstanding electronic properties. Despite the promise, this method still faces potential challenges, including achieving consistent device quality and maintaining process control during large-scale manufacturing.
CMOS BEOL-compatible integration of GaN HEMTs and micro-LEDs on 2D/CMOS substrate. a) 3D illustration (left) and cross-sectional schematic (right) of a monolithically integrated system achievable via FAST technology, which allows the direct stacking of CMOS, 2D, and III-N layers. The layers shown in transparent colors imply that other 2D layers or III-V compound semiconductor layers (e.g., InGaAs) can be also integrated. Via FAST, vertical and lateral integration of III-V devices is possible, if only the interposer structure can be fabricated. b) 3D schematic illustrations and epitaxial structures of AlGaN/GaN HEMT (top) and GaN-based micro-LED (bottom). c) Schematic illustration of the integration process of III-N devices on a 2D/CMOS substrate. 2D materials were transferred onto the CMOS substrate via BEOL-compatible process. (Image: Reprinted with permission by Wiley-VCH Verlag) (click on image to enlarge)
GaN is particularly appealing for electronic applications due to its efficiency and robustness, especially in high-frequency, high-power scenarios. However, integrating GaN devices directly onto silicon substrates historically faced problems due to incompatibilities in thermal expansion and lattice structures, causing device instability and reduced performance. The FAST method mitigates these issues by using an atomically flat buffer layer of aluminum nitride (AlN), compatible with both GaN and the 2D substrates employed in this research.
A significant innovation was the development of a rotationally symmetric transistor design for GaN devices, simplifying alignment during transfer. Combined with FAST’s precise control, integration accuracy reached within tens of nanometers, demonstrating robust capability suitable for industrial-scale application. Integration testing across standard 200 mm silicon wafers, an industry standard, underscored the process’s practicality and scalability.
Tests confirmed that these vdW-integrated devices maintain performance characteristics comparable to conventionally fabricated devices, essential for commercial viability. Electrical testing verified stable transistor characteristics, reliable threshold voltages, low leakage currents, and effective heat dissipation. The graphene layer served a dual purpose: as an efficient heat dissipator due to its superior thermal conductivity and as an electrical interconnect by providing conductive pathways for signals between integrated components, enhancing overall system integration.
Further validation included integrating these III-Nitride devices onto silicon-on-insulator (SOI) substrates. SOI technology is widely used in integrated circuits for its superior performance characteristics, particularly in radio-frequency (RF) applications. Successfully integrating GaN-based RF power and cascode transistors onto SOI substrates using FAST reinforces the technology’s practical viability for advanced electronics.
This approach is notable for its versatility, capable of integrating other III–V semiconductors, thus broadening potential applications beyond GaN. Possible future applications include advanced silicon photonics—optical communication systems integrated onto silicon chips—high-speed electronics, and quantum computing technologies, all essential for next-generation electronic systems.
The FAST integration method and resulting semiconductor devices represent a significant step toward overcoming silicon’s limitations. Combining high-performance 2D materials with robust III-Nitride devices through CMOS-compatible processes points toward new horizons in semiconductor design and integration.
This aligns with the industry’s “More than Moore” strategy, focusing on diversified technological innovations beyond merely shrinking device size. The developments presented here promise substantial advancements, enabling more powerful, efficient, and multifunctional electronic systems, crucial for future technological progress.
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